1. Field of the Invention
The present invention relates to a method and apparatus for generating a variable delay clock and in particular to a system of controlling the delay of a clock with high resolution in the delay.
2. Description of the Related Art
There are several methods to delay a clock signal. One method to delay a clock is to insert a delay buffer, such as a CMOS delay buffer, in the clock signal. A CMOS delay buffer typically comprises two CMOS inverters, each of which can comprise a NMOS transistor and a PMOS transistor. The delay to the clock caused by the buffer depends on many factors, including the clock speed, the transistor sizes, the supply voltage, and the temperature. Therefore, it is very difficult to accurately control the delay using a simple delay buffer.
For high-speed applications, current mode logic (CML) is usually used in lieu of CMOS logic. CML is typically implemented in differential circuit configuration. A CML delay buffer can comprise, for example, a single differential transistor pair, a biasing transistor, and a pair of load transistors. Unlike the above-mentioned CMOS buffer, the delay caused by CML delay buffer can be controlled by adjusting the bias voltages. However, the delay still cannot be accurately controlled unless the bias voltages are adjusted in a close-loop manner. In a typical embodiment, a delay lock loop (DLL) is used to perform the close loop control of a delay buffer.
The DLL circuit uses a clock multiplex circuit to implement a variable delay. However, a high frequency clock multiplexer is difficult to design, especially when the number of inputs is high. The multiplexer selects among N clocks of different phases generated by an N-stage DLL. The resolution of the delay depends on the number of stages of delay buffers. In general, an N-stage DLL has a resolution of 180/N degree in phase delay. To achieve a 10-degree resolution of phase delay, for example, it takes an 18-stage DLL. Therefore, it is impractical to use DLL to generate a variable delay clock with high resolution in the phase delay.